(a) Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a gate to which different voltages are applied and a method for fabricating the semiconductor device.
(b) Description of the Related Art
As semiconductor devices have been implemented for various applications, different device characteristics are required. For example, there can be a device such as a logic and central processing unit (CPU) merged with Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Accordingly, a high voltage device and low voltage device are formed in a single substrate.
The operation voltage of the chip varies according to the characteristics of respective devices integrated in the single chip. Thus, even though some components perform identical functions, their volume and size differ from each other according to the input voltages.
FIG. 1 is a cross sectional view illustrating a conventional CMOS of a high voltage region.
Referring to FIG. 1, P and N wells 102 are formed in an active region defined by a device isolation region 110 which is formed by filling a trench (T) formed within a substrate 100. Below the device isolation region 110, channel stop regions 112 are formed by doping the impurity ions of a type identical to those of the wells 102, respectively.
An NMOS transistor is formed in the P well of the high voltage region. An active region divided by the device isolation region 110 and a PMOS transistor is formed in the N well. In the drawing only a gate 114 and a gate dielectric layer 113 of the respective thin layer transistor are depicted. The channel stop regions 112 are positioned below the device isolation region between the P type transistor and the N type transistor and prevent the two devices from affecting each other.
However, the conventional method has drawbacks in that the fabrication processes are so complicated. The conventional processes are also limited in miniaturizing the size of the device, because the sizes of the device isolation region and the active region should be designed in consideration of the channel stop region.